Dr. V. Ramesh Kumar
Assistant Professor
Office Address:
323, 2nd Floor, Academic Building
Department of Electronics and Communication Engineering Group
Indian Institute of Information Technology -Sri City, Chittoor, Andhra Pradesh-517 646, India
Academic Qualifications
Education:
PhD [Microelectronics and VLSI Design], 2016
Department of Electronics and Communication Engineering,
Indian Institute of Technology Roorkee, India
Thesis Title: Modeling of Crosstalk Effects in CMOS Gate Driven On-Chip Interconnections Using FDTD Technique
M.Tech [VLSI Design Automation & Techniques], 2010
Department of Electronics and Communication Engineering,
National Institute of Technology Hamirpur, India
Thesis Title: Design of Reconfigurable Multipliers for Integer and Galois Field Multiplications
Department of Electronics and Communication Engineering,
Indian Institute of Technology Roorkee, India
Thesis Title: Modeling of Crosstalk Effects in CMOS Gate Driven On-Chip Interconnections Using FDTD Technique
M.Tech [VLSI Design Automation & Techniques], 2010
Department of Electronics and Communication Engineering,
National Institute of Technology Hamirpur, India
Thesis Title: Design of Reconfigurable Multipliers for Integer and Galois Field Multiplications
Research Areas of Interest
VLSI Circuit Design, Device Modeling, On-chip Interconnections, Ternary Logic Circuits, Carbon Nano Transistors and Interconnections, Through Silicon VIAs
Awards / Honours
IEEE Student Travel Grant-INIS
Listed in Marquis Who’s Who in the World in 2016
IEEE Senior Member
Listed in Marquis Who’s Who in the World in 2016
IEEE Senior Member
Projects
Design of CNT based Through Silicon VIAs for a Realistic 3D Integrated Circuits, SERB, Department of Science and Technology, Early Carrier Research Award, Total Budget Rs. 39,60,990/-
Publications
List of Publications
International Transactions/Journals/Magazines
- V. Ramesh Kumar, S. J. Basha, P. Venkataramana, M. D. Prasad and L. Ujwala (2021), "Design of bilayer graphene nanoribbon tunnel field effect transistor", Circuit World, Early Access, August 2021.
- B. Divya Madhuri, S. Sunithamani, S.J. Basha, and V. Ramesh Kumar “Design of Hardened Flip-flop using Schmitt Trigger-Based SEM Latch in CNTFET Technology,” Circuit World, vol 47, no. 1, pp. 51-59, June, 2020.
- S.J. Basha, and V. Ramesh Kumar, “Design of MWCNT based Through Silicon Vias with Polymer Liners to Reduce the Crosstalk Effects,” ECS Journal of Solid State and Technology, vol. 9, pp. 041002, 1-5, April 2020.
- A. Kumar, V. Ramesh Kumar. B. K. Kaushik, “Transient Analysis of Crosstalk Induced Effects in Mixed CNT Bundle Interconnects Using FDTD Technique” IEEE Trans. on Electromagnetic Compatibility, vol. 61, no. 5, pp. 1621-1629, Oct. 2019.
- KTN Jyothi, V. Sulochana, V. Ramesh Kumar, K. S. Rao, “Modeling of CMS‐based nonuniform interconnects using FDTD technique” International Journal of Circuit Theory and Applications, Wiley, vol. 47, pp. 43–54, Oct. 2018.
- C. Reddy, C. Venkataiah, V. Ramesh Kumar, S. Maheshwaram, N. Jain, S. Dasgupta, and S. K. Manhas, “Design and Simulation of CNT Based Nano-Transistor for Greenhouse Gas Detection” Journal of Nanoelectronics and Optoelectronics, vol.13, no. 4, pp. 593-601, April 2018.
- V. Ramesh Kumar, A. Alam, B. K. Kaushik, and A. Patnaik, “An unconditionally stable FDTD model for crosstalk analysis of VLSI interconnects,” IEEE Transactions Components, Packaging and Manufacturing Technology, vol. 5, no. 12, pp. 1810-1817, Dec. 2015.
- V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “Improved Crosstalk Noise Modeling of MWCNT Interconnects Using FDTD Technique,” Microelectronics Journal (Elsevier) vol. 46, no. 12, pp.1263-1268, Dec. 2015.
- M. K. Majumder, P. K. Das, V. Ramesh Kumar, and B. K. Kaushik “Crosstalk induced delay analysis of randomly distributed mixed CNT bundle interconnect,” Journal of Circuits, Systems and Computers (World Scientific), vol. 24, no. 10, pp. 1550145-1–1550145-15, Dec. 2015.
- V. Ramesh Kumar, M. K. Majumder, A. Alam, N. R. Kukkam, and B. K. Kaushik, “Stability and delay analysis of multi-layered GNR and multi-walled CNT interconnects,” Journal of Computational Electronics (Springer), vol. 14, no. 2, pp. 611-618, June 2015.
- V. Ramesh Kumar, M. K. Majumder, N. Kukkam, and B. K. Kaushik, “Time and frequency domain analysis of MLGNR interconnects,” IEEE Transactions Nanotechnology, vol. 14, no. 3, pp. 484-492, May 2015.
- V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “Crosstalk noise modeling of multiwall carbon nanotube (MWCNT) interconnects using finite-difference time-domain (FDTD) technique,” Microelectronics Reliability (Elsevier), vol. 55, no. 1, pp. 155-163, Jan. 2015.
- M. K. Majumder, J. Kumar, V. Ramesh Kumar, and B. K. Kaushik, “Performance analysis for randomly distributed mixed carbon nanotube bundle interconnects,” IET Micro & Nano Letters, vol. 9, no. 11, pp. 792-796, Dec. 2014.
- V. Ramesh Kumar, M. K. Majumder, and B. K. Kaushik, “Graphene based on-chip interconnects and TSVs – Prospects and challenges,” IEEE Nanotechnology Magazine, vol. 8, no. 4, pp. 14-20, Nov. 2014.
- B. K. Kaushik, M. K. Majumder, and V. Ramesh Kumar, “Carbon nanotube based 3-D interconnects - A reality or a distant dream,” IEEE Circuits and Systems Magazine, vol.14 no. 4, pp. 16-35, Nov. 2014.
- V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “An accurate FDTD model for crosstalk analysis of CMOS-gate-driven coupled RLC interconnects,” IEEE Transactions Electromagnetic Compatibility, vol. 56, no. 5, pp. 1185-1193, Oct. 2014.
- V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method,” Microelectronics Journal (Elsevier), vol. 45, no. 4, pp. 441-448, April 2014.
International/National Conferences/Symposiums
- G. Mounika and V. Ramesh Kumar, “Design of Novel Through Silicon via Structures for Reduced Crosstalk Effects in 3D IC Applications,” in Proc. Intelligent Communication, Control and Devices (Springer), Dehradun, pp. 599-605, April 2018.
- Y. Ramesh and V. Ramesh Kumar, “Effect of Skin Impedance on Delay and Crosstalk in Lossy and Non-uniform On-Chip Interconnects,” in Proc. Intelligent Communication, Control and Devices (Springer), Dehradun, pp. 569-576, April 2018.
- V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “Accurate Numerical Model for Crosstalk Analysis of SWCNT Bundle Interconnects Using FDTD Method,” in Proc. IEEE International Symposium on Nanoelectronic and Information Systems, Indore, pp.158-163, Dec., 2015.
- M. K. Majumder, A. Kumari, A. Alam, V. Ramesh Kumar and B. K. Kaushik, “Signal integrity improvement with peripherally placed MWCNTs in mixed CNT bundle based TSVs,” in Proc. IEEE Conference on Electron Devices and Solid-State Circuits, Singapore, pp. 649-652, June, 2015.
- V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “Crosstalk modeling with width dependent MFP in MLGNR interconnects using FDTD technique,” in Proc. IEEE Conference on Electron Devices and Solid-State Circuits, Singapore, pp. 138-141, June 2015.
- A. Alam, M. K. Majumder, A. Kumari, V. Ramesh Kumar, and B. K. Kaushik, “Performance analysis of single- and multi-walled carbon nanotube based through silicon vias,” in Proc. IEEE Electronic Components and Technology Conference (ECTC), Marina San Diego, USA, pp. 1834-1839, May 2015.
- V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “Modeling of crosstalk effects in coupled MLGNR interconnects based on FDTD method,” in Proc. IEEE Electronic Components and Technology Conference (ECTC), Florida, USA, pp. 1091-1097, May 2014.
- V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “Dynamic crosstalk analysis of CMOS driven RLC interconnects using FDTD method,” in Proc. IEEE Radio Science Meeting AP-S/USNC-URSI, Florida, USA, p.80, July 2013.
- V. Ramesh Kumar, B. K. Kaushik, and A. Patnaik, “Performance comparison of multilayer graphene nanoribbon and copper based VLSI interconnects,” Presented in Nano India 2013, Trivandrum, Feb. 2013.
Books/Chapters
- B. K. Kaushik V. Ramesh Kumar, M. K. Majumder, and A. Alam “Through Silicon Vias – Materials, Models, Design and Performance,” CRC Press, Taylor & Francis, 2016, ISBN 9781498745529.
- B. K. Kaushik, V. Ramesh Kumar, and A. Patnaik, “Crosstalk in Modern On-Chip Interconnects: A FDTD Approach,” Springer Briefs in Applied Sciences and Technology, Springer Singapore, 2016, ISBN 978-981-10-0800-9.
- V. Ramesh Kumar, S. J. Basha, B. D. Madhuri and S. Sunithamani, “Design of Through Silicon Vias for Improved Performance in 3D IC Applications” IET Book Chapter, September 2019, ISBN: 9781839530548
- V. Ramesh Kumar, Vobulapuram, M. Lohith, S. Basha, R. Reddy, “Bilayer Graphene Nanoribbon Tunnel FET for Low-Power Nanoscale IC Design,” Springer Singapore, 2020, ISBN: 978-981-15-7937-0
Students
Teaching
VLSI Design
Electronic Devices
Electronic Circuit Analysis
Electronic Devices
Electronic Circuit Analysis
Contact Information
Address for Communication:
323, 2nd Floor, Academic Building
Department of Electronics and Communication Engineering Group
Indian Institute of Information Technology -Sri City, Chittoor, Andhra Pradesh-517 646, India
